As known, the need of nonvolatile memories with ever larger densities leads to the design of multilevel memories wherein the data, stored in the floating gate regions of the cells, are coded on several logic levels, dividing up the quantity of charge stored in each cell.
FIG. 1 shows the characteristic linking the gate-source voltage V.sub.gs to the drain-source current I.sub.ds of a flash cell for a two level memory, i.e., wherein data are coded in each cell of the memory by a bit having two possible values, associated respectively with an on or off condition of the cell, in its turn depending on the programmed or not state of the cell. In particular, in FIG. 1 V.sub.tv and V.sub.tw represent the value of the gate-source voltage V.sub.gs at which a flash cell begins to conduct current, for virgin (erased) cell and written cell respectively. In a memory of this type, generally the characteristic having threshold voltage V.sub.tv, normally between 1 and 2.5 V, is assigned to the logic value "1", and the characteristic having threshold voltage V.sub.tw, generally greater than 5 V, is assigned to the logic value "0".
It is also known that reading a memory cell consists in converting the current absorbed by the memory cell, at a given gate-source voltage V.sub.gs, into a voltage then translated to a CMOS output level by a suitable comparator circuit. An example of a known reading circuit is shown in FIG. 2; the reading circuit 1 comprises a current/voltage converter (formed by a current mirror circuit 2) and a comparator 3; the current mirror circuit 2 has two nodes respectively connected to a memory cell 4 and to a reference cell 5 and to the inputs of the comparator 3, the output of which supplies the CMOS level signal coding the bit read.
In case of multilevel cells, the plane (V.sub.gs, I.sub.ds) is subdivided by several characteristics, as shown in FIG. 3 for example, relating to the storage of two bits per cell, corresponding to four logic values "11","10", "01" and "00". Here the four logic values correspond to four different threshold values Vt1, Vt2, Vt3 and Vt4, in their turn linked to different quantities of charge stored in the floating gate region of the memory cells.
Cell programming is affected by uncertainty and the characteristics of both FIG. 1 and FIG. 3 represent the central value of the distributions that can actually be obtained; in practice, each threshold value is associated to a respective distribution of values comprised between a minimum and a maximum value sufficiently spaced from the maximum value of the preceding distribution and/or from the minimum value of the subsequent distribution to enable the cell to be correctly read. Furthermore, each distribution may exhibit a different amplitude, as shown in FIG. 4 for example, showing the distributions associated with memory cells each storing two bits and in which the scale is not uniform.
In this case also, reading consists of converting the current flowing in the cell into a voltage; the voltage thus obtained is then compared with various voltage values intermediate between the threshold distributions discussed above.
One of the problems arising in case of multilevel cell reading is linked to the reading voltage applied to the gate terminals of the cells to be read; at the selected reading voltage, all the read cells (possibly except the cells programmed at the highest threshold value) must be on, to be able to compare the converted voltage with the different voltage levels; consequently, the reading voltage must be at least greater than the penultimate threshold value (V.sub.t3 in FIG. 3; V.sub.R in FIG. 4, equal to 6 V here).
FIG. 5 shows the variability intervals of the characteristics, taking account of the distributions of the threshold voltages shown in FIG. 4 and three reference current values I.sub.R1, I.sub.R2, I.sub.R3 compared with the current flowing in the memory cells at the reading voltage V.sub.R. In practice, the three reference current values have an intermediate value between the various distributions of characteristics.
According to an embodiment, at the reading voltage V.sub.R of 6 V, the distribution of currents associated with the logic level "11" varies between 70 and 85 .mu.A, the distribution of currents associated with the logic level "10" varies between 40 and 50 .mu.A, the distribution of currents associated with the logic level "01" varies between 10 and 20 .mu.A, and the cells storing the logic level "00" are off. The reference currents I.sub.R1, I.sub.R2, I.sub.R3 are therefore equal to 60, 30 and 5 .mu.A respectively.
FIG. 6 shows an example of a reading logic circuit 10 generating two bits 01, 02 stored in a cell, after comparison with three reference voltages V.sub.1, V.sub.2, V.sub.3 corresponding to the reference current values I.sub.R1, I.sub.R2, I.sub.R3 of FIG. 5, wherein V.sub.1 &lt;V.sub.2 &lt;V.sub.3. In detail, the reading logic circuit 10 comprises three comparators 11, 12, 13, receiving, at the noninverting inputs, a same voltage V.sub.m resulting from the conversion of the current flowing in a read memory cell and, at the inverting inputs, a respective reference voltage V.sub.1, V.sub.2, V.sub.3. The output of the comparator 11 is connected to a first input of a first AND gate 14 with three inputs; the output of the comparator 12 defines a first output 15 of the reading logic circuit 10 and is connected to a second input of the first AND gate 14 through a first inverter 16; the output of the comparator 13 is connected to a third input of the first AND gate 14 and to an input of a second AND gate 17 with two inputs. The output of the first AND gate 14 is connected to a second input of the second AND gate 17 through a second inverter 18. In this way, the output 15 of the reading logic circuit 10 supplies the first bit 01; the output of the second AND gate 17 defines a second output 19 of the reading logic circuit 10 and supplies the second bit 02.
The memory cells of the type under consideration have small gain (20 .mu.A/V); furthermore, existing architectures require that the reading voltage V.sub.R (the minimum value of which is limited by the distributions of the threshold voltages, as explained above) be not too high (no greater than 6 V for example). These conditions present a problem when reading cells storing four levels (two bits); in fact, it is necessary to discriminate between currents different from each other by 10 .mu.A but having different common mode contributions, given that the difference between the various currents is always selected to be equal to 10 .mu.A, but the absolute value varies between 0 and 70 .mu.A. Discrimination is also rendered more complex by the variations in gain associated with the different threshold voltages.